Senior FPGA Engineer Verified today

About Aerospacelab

Aerospacelab designs and manufactures small satellites combined with earth observation services. Founded in 2018, the company now has over 200 full-time employees across offices in Louvain-la-Neuve (Belgium), Toulouse (France), Lausanne (Switzerland) and the US West Coast.

The Role

Contemporary satellites are constructed in modular units, each dedicated to a specific function. Aerospacelab designs a wide variety of FPGA-based units that form the foundation of these modules.

As Senior FPGA Engineer, you will take technical ownership of gateware across our growing FPGA portfolio. You will join an agile development team focused on a specific unit: on-board computers, software-defined radios, image sensors, optical transceivers, network switches or telecommunication payload. You will act as the FPGA technical reference for your team.

Key Responsibilities

• Define and own FPGA design architecture from system requirements, including major design trade-offs
• Design, simulate, integrate and test RTL code while reviewing the RTL of others
• Drive verification strategy: testbenches, on-target test procedures, and CI
• Write and test software driver code
• Write and review technical documentation
• Mentor junior and mid-level engineers, and lead small FPGA teams on complex units
• Interface with other engineering teams (EE, RF, Operations, Embedded Software, System) and represent FPGA in cross-unit technical decisions
• Answer challenging requirements with innovative, well-justified architectural solutions
• Cope with the constraints of the space environment
• Create critical, high-quality gateware and verification
• Set and uphold design, documentation and verification standards across the team

Your Background

• 5 to 10 years professional experience in FPGA/RTL design, with track record from requirements through validated hardware
• Master or PhD in Computer, Electronics or Mechatronics Engineering or equivalent through experience
• Strong command of RTL programming (VHDL, Verilog, SystemC, SystemVerilog)
• Experience with C and Python
• Strong understanding of full FPGA design flow (synthesis, place and route, timing closure)
• Strong understanding of software and hardware interactions
• Solid experience with version control and continuous integration
• Experience with digital signal or image processing
• Proven ability to mentor engineers and provide technical leadership
• Excellent verbal and written communication skills
• Comfortable in lab environment: power supplies, oscilloscopes and spectrum analyzers
• Good English knowledge
• Passion for digital design

Nice To Have

• Experience in space or high-reliability/safety-critical domain (avionics, automotive, medical)
• Familiarity with radiation effects and mitigation techniques (TMR, scrubbing)
• Experience with Embedded-Linux (CLI usage and kernel customization)
• Experience with high-speed transceivers, PCIe or network interfaces (1G to 100G)
• Experience with memory interfaces (DDR3, DDR4, DDR5)
• Experience with PCB and hardware design
• Experience with advanced or formal verification methodologies

Work Environment

• RTL: VHDL
• Simulation: Questasim, Makefile, Python, TCL
• Tests on target: Makefile, Embedded-C, Embedded-Linux, FreeRTOS, Python
• CI/CD: Gitlab, Docker