Senior High-Speed PCB Layout Engineer Verified today

About Array Labs

Array Labs builds advanced radar systems for earth observation. We're launching a coordinated fleet of radar satellites to create a high-resolution 3D map of the Earth, updated in real time, enabling faster decision-making for disaster response, infrastructure resilience, and geopolitical intelligence.

The Role

As a Senior High-Speed PCB Layout Engineer, you will own the physical implementation of Array's high-speed digital and mixed-signal electronics in Altium, translating schematics and performance requirements into layouts and functional designs. The boards you ship will directly determine signal integrity, power integrity, noise performance, and overall system reliability in the lab and on orbit.

Your Responsibilities

• Own high-speed PCB layout from initial placement through manufacturing release in Altium
• Define and implement stack-ups, impedance targets, length-matching constraints, and reference plane/return-path strategies for high-speed interfaces
• Translate schematic intent into layouts that meet signal integrity and power integrity requirements across mixed-signal and digital domains
• Partner with electrical design, firmware, mechanical, and test engineers to develop layout constraints, run reviews, and de-risk first-pass success
• Drive DFM/DFT considerations with fabrication and assembly partners, including documentation and release artifacts

Basic Qualifications

• B.S. in Electrical Engineering or related field with 4+ years of relevant experience
• Experience in PCB layout, fabrication, and release of high-speed digital and mixed-signal electronics
• Excellent teamwork and communication skills
• Ability to learn new concepts rapidly and self-direct
• High levels of self-motivation and personal accountability
• Ability to work in a fast-paced environment under time constraints

Preferred Skills and Experience

• Hands-on experience designing high-speed digital and mixed-signal PCB layouts including constraint-driven routing, impedance control, and length matching
• Expert-level proficiency with Altium Designer for complex layout and clean manufacturing outputs; familiarity with Allegro and/or OrCAD
• Experience developing PCB stack-ups and layout constraints for high-speed interfaces and dense, high-performance boards
• Strong intuition for layout-driven SI/PI behavior, including return paths, reference plane strategy, via transitions, and noise coupling between domains
• Experience working closely with electrical design engineers to translate schematic intent into first-spin layouts
• Experience with manufacturing release, DFM/DFT considerations, and collaborating with fabrication and assembly partners
• Experience supporting lab bring-up and debug alongside design and test engineers, including investigating SI/PI issues on hardware
• Familiarity with SI/PI analysis workflows and tools such as Ansys SIwave, Keysight Power Analyzer, HyperLynx, or Sigrity
• Experience taking high-performance hardware from prototype through qualification and environmental testing

ITAR Requirements

To conform to U.S. Government space technology export regulations, you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.

Compensation and Interview

Competitive pay with high flexibility between salary and equity-based compensation. Interviews conducted via Google Meet; typical process takes 2-4 weeks.