ASIC Engineer - Early Career Verified today
About This Role
Multiple positions available across Blue Origin business units. You will be matched with an engineering team based on your skillset and current business needs. We prioritize co-locating early career engineers with their teams and the hardware they support.
What You'll Do
- Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs
- Support module-level and subsystem-level verification using SystemVerilog/UVM
- Write test plans and functional coverage definitions under guidance from senior team members
- Assist with CDC/RDC/LINT checks and clean-up
- Participate in code coverage and functional coverage closure activities
- Help develop assertions, protocol monitors, and scoreboards for testbenches
- Support integration and verification of external IP (e.g., bus fabrics, standard interfaces)
- Learn and apply industry-standard verification methodologies (UVM, formal verification basics)
- Debug RTL and testbench issues with guidance from senior engineers
- Document design intent, verification results, and test coverage
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year)
- Coursework or project experience with Verilog/SystemVerilog RTL design or verification
- Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing)
- Familiarity with basic verification concepts (testbenches, simulation, coverage)
- Strong problem-solving skills and attention to detail
- Effective communication and ability to work in a collaborative team environment
Desired Experience
- Academic or internship experience with SystemVerilog/UVM
- Exposure to scripting languages (Python, Perl, Tcl) for automation/tooling
- Coursework or projects involving communications systems, DSP, or FPGA design
- Familiarity with common EDA tools (e.g., VCS, Xcelium, Questa, formal tools)
- Understanding of computer architecture fundamentals (CPUs, bus protocols like AXI)
- Personal projects, capstone work, or research involving digital design/verification (e.g., GitHub repos, senior design projects)
Compensation
Base pay range for CA and WA applicants: $129,032.00 - $180,644.10. Other site ranges may differ.
Employment Requirements
Applicants must be a U.S. citizen or national, U.S. permanent resident (Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Benefits
- Medical, dental, vision, basic and supplemental life insurance
- Paid parental leave
- Short and long-term disability
- 401(k) with company match up to 5%
- Education Support Program
- Stock options for all regular employees (working at least 20 hours/week)
- Up to four weeks paid time off per year and up to 14 company-paid holidays
- Eligibility for bonuses based on role type and job level
Application Timeline
Applications will be reviewed on a rolling basis. Close date: 02/12/2027.