ASIC Engineering Director Verified today

Blue Origin · Kraków, Poland · Electronics · first seen 2026-09-03

About the role

Blue Origin is pioneering TeraWave, a revolutionary satellite communications network delivering symmetrical data speeds of up to 6 Tbps using optically interconnected satellites in low and medium Earth orbit.

You will establish and lead the ASIC engineering organization in Kraków, Poland. The team will emphasize design verification while developing capabilities in front-end design, digital architecture, implementation, embedded hardware integration, and selected digital-top mixed-signal functions. You will serve as the Kraków engineering site leader with responsibility for the shared ASIC and prototype integration laboratory.

What you will own

Establish, lead, and grow the Kraków ASIC engineering organization from initial focus on design verification into front-end design and digital functions.
Define technical strategy, staffing plan, operating model, engineering processes, and development roadmap.
Recruit, develop, mentor, and retain engineering managers, technical leads, staff engineers, and individual contributors.
Lead ASIC development across the product lifecycle: requirements, architecture, RTL design, verification, implementation, tape-out, silicon bring-up, and qualification.
Own program execution: scope, schedule, quality, staffing, resource planning, and risk management.
Establish scalable ASIC verification methodologies and infrastructure for block-, subsystem-, and SoC-level verification, including requirements traceability, test planning, functional and code coverage, assertions, formal verification, emulation, FPGA prototyping, gate-level simulation, and regression management.
Support digital front-end capabilities: RTL design, microarchitecture, CDC/RDC, lint, clocking, low-power and multi-voltage design, interface integration, and design quality.
Provide technical oversight for integration of complex digital and communication SoCs, including processors, bus fabrics, DMA, NoCs, memory controllers, high-speed interfaces, external IP, and analog/mixed-signal macros.
Guide development and verification of DSP-intensive communication systems: modem architectures, coding, framing, PHY and MAC functions, FIR filters, CORDIC, FFT/IFFT, MAC engines, circular buffers, and time-bound data movement.
Promote use of golden reference models and cross-domain verification using MATLAB, SystemC, C/C++, Python, and SystemVerilog.
Ensure robust verification of digital-top mixed-signal systems through behavioral models, co-simulation, analog macro abstraction, and system-level validation.
Partner with analog/mixed-signal and RF leaders on specifications, interfaces, models, integration plans, and verification strategies.
Support implementation, DFT, LEC, floorplanning, static timing analysis, power analysis, physical verification, and signoff activities.
Establish effective flows between ASIC and FPGA implementations, emulation, prototyping, pre-silicon verification, and post-silicon validation.
Partner with software and firmware teams on hardware/software co-simulation, processor integration, boot flows, drivers, diagnostics, and system-level validation.
Participate in silicon bring-up, characterization, failure analysis, root-cause investigation, and corrective action.
Lead technical reviews, architecture assessments, design reviews, verification reviews, and lessons-learned activities.
Serve as accountable engineering leader for the Kraków ASIC and prototype integration lab, with technical leads supporting design verification, software, firmware, and RF/mixed-signal engineering.
Ensure shared lab infrastructure effectively supports FPGA prototyping, hardware-in-the-loop testing, embedded software and firmware integration, modem and digital beamformer development, and system-level debug.
Establish processes for lab planning, equipment configuration, prototype tracking, test automation, data management, maintenance, calibration, safety, and infrastructure reliability.
Partner with facilities, IT, security, procurement, and EHS teams on lab operations, equipment procurement, physical infrastructure, access controls, and safe operation.
Manage lab capacity and capital planning aligned with program priorities and organizational growth.
Develop strong working relationships with engineering leaders and stakeholders in Kraków and across Blue Origin's global organization.
Represent the Kraków ASIC organization in program reviews, planning activities, technical forums, and executive discussions.
Establish a collaborative, inclusive, and high-performing Kraków engineering site culture in partnership with other functional leaders.
Support local site operations, workforce planning, employee development, engineering communications, and cross-functional coordination.
Travel as required to support collaboration with other Blue Origin locations, suppliers, technology partners, and program teams.

Minimum Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
15+ years of relevant experience in ASIC, SoC, semiconductor, or complex digital system development.
8+ years of experience leading engineering organizations, including responsibility for hiring, team development, execution, and technical direction.
Demonstrated experience leading the development and delivery of complex ASICs or SoCs through tape-out and silicon bring-up.
Significant experience with design verification of complex SoCs using SystemVerilog and modern verification methodologies.
Strong understanding of verification planning and closure, including functional coverage, code coverage, assertions, formal verification, regressions, emulation, FPGA prototyping, gate-level simulation, and software co-simulation.
Experience leading teams responsible for block-, subsystem-, and full-SoC verification.
Strong understanding of digital front-end design and ASIC implementation flows, including RTL design, CDC/RDC, lint, timing constraints, clocking, low-power or multi-voltage design, DFT, LEC, floorplanning, static timing analysis, and power analysis.
Experience integrating complex SoC components, such as processors, cache and memory subsystems, MMUs, interrupt controllers, secure boot, bus fabrics, AXI, DMA, NoCs, and external IP.
Experience with high-speed and system interfaces such as DDR, PCIe, Ethernet, SPI, and high-speed SerDes.
Experience with DSP-intensive systems and/or modern communication SoCs, including modem, PHY, MAC, coding, framing, and high-throughput data movement.
Demonstrated ability to define requirements, specifications, development plans, verification plans, schedules, and technical milestones.
Experience building or operating a hardware, ASIC, FPGA, embedded systems, RF, or system-integration laboratory.
Experience with hardware-in-the-loop testing, FPGA prototyping, lab automation, or automated hardware regression infrastructure.
Fluency in English is required.

Preferred Qualifications

MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Experience building a new ASIC or semiconductor engineering organization or establishing a new engineering site.
Experience leading organizations spanning design verification, RTL/front-end design, digital architecture, emulation, FPGA prototyping, and post-silicon validation.
Deep experience with communication SoCs, modem architectures, wireless or satellite communications, RF systems, or other DSP-intensive products.
Experience with DSP architectures including FIR, CORDIC, FFT/IFFT, MAC, channelization, sample-rate conversion, circular buffers, and analog-to-digital interfaces.
Experience with deterministic latency, time-slotted systems, timestamping, and real-time data processing.
Experience developing reusable verification environments and portable verification flows across simulation, emulation, FPGA, pre-silicon, and silicon environments.
Experience integrating software build flows with simulation, FPGA, emulation, and verification environments.
Experience qualifying FPGA prototypes or emulation platforms and partitioning verification across simulation, emulation, and prototyping.
Experience with digital-top mixed-signal SoCs, including analog macro modeling, AMS co-simulation, mixed-mode verification, and top-level integration.
Familiarity with analog/mixed-signal design and verification flows and tools such as Cadence Virtuoso, Spectre, AMS, MATLAB, and SystemVerilog-AMS.
Experience collaborating with analog, RF, PLL, data converter, power management, and other mixed-signal design teams.
Experience with silicon characterization, post-silicon debug, production test, and yield improvement.
Experience managing external IP vendors, design partners, EDA providers, foundries, and technology partners.
Experience establishing shared engineering lab processes, including equipment procurement, asset tracking, configuration management, calibration, maintenance, and safety.
Experience with lab automation using Python, SCPI, MATLAB, LabVIEW, or comparable tools.
Experience supporting conducted RF link closure, modem validation, digital beamformer testing, or communications-system integration.
Demonstrated experience developing engineering managers and senior technical leaders.
Strong technical judgment and the ability to balance performance, power, area, schedule, quality, cost, and risk.
Demonstrated ability to lead through influence across geographically distributed and cross-functional teams.
Demonstrated ability to lead through functional technical leads across multiple engineering disciplines.
Experience working in a highly regulated, safety-critical, aerospace, defense, communications, or other high-reliability environment.
Excellent written, verbal, and interpersonal communication skills.
Fluency in Polish or experience working effectively within Polish engineering organizations.