Principal ASIC DFT Design Engineer - Terawave Verified today

About the role

As Principal ASIC DFT Designer on the ASIC Engineering SOC Team, you will own design for test architecture for the TeraWave System on Chip (SOC) program. This is a senior individual contributor role with technical leadership scope and no direct reports. Your work spans specification through silicon bring up, including ATE pattern debug and support for defect and yield analysis, and it directly determines test quality and manufacturability for the program.

TeraWave is Blue Origin's revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth, servicing tens of thousands of enterprise, data center, and government users.

Responsibilities

• Define DFT architecture and test strategy for large multi-block SOC designs
• Author DFT specifications covering scan, compression, boundary scan, and test access mechanisms
• Implement scan chain insertion, test clock control, and on-chip compression logic
• Design memory and logic built-in self test infrastructure for embedded memories and logic
• Generate and validate DFT vectors for silicon bring up and production test programs
• Debug ATE pattern failures and drive resolution with design and product engineering teams
• Support defect analysis and yield improvement using test coverage and silicon failure data
• Review test coverage and DFT timing metrics with physical design and verification teams

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• Minimum 10 years of experience in design for test for complex digital SOCs
• Experience defining DFT architecture and specifications for large multi-block SOC designs
• Experience with DC and AC scan design and memory built-in self test implementation
• Experience generating ATPG patterns for automated test equipment and debugging ATE patterns

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related technical field
• Experience with logic built-in self test implementation and signature-based test methodologies
• Experience with defect analysis and yield improvement for advanced process node silicon
• Experience with hierarchical DFT and IEEE 1500 or IEEE 1687 test access standards
• Experience with commercial DFT tool flows such as Tessent, DFTMAX, or Modus
• Experience with test time and test cost reduction through pattern and compression optimization
• Strong written and verbal communication skills for presenting test strategy to technical stakeholders

Compensation

Base pay range for CA and WA applicants: $269,175.00 - $376,843.95. Other site ranges may differ.

Requirements

Applicants for employment at Blue Origin must be a U.S. citizen or national, U.S. permanent resident (i.e. current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Required background checks: Blue's Standard Background Check. Additional checks may apply based on role requirements, including DBIDS background check if the role requires access to military installations.

Benefits

• Medical, dental, vision, basic and supplemental life insurance
• Paid parental leave
• Short and long-term disability
• 401(k) with company match of up to 5%
• Education Support Program
• Stock options for all regular employees (working at least 20 hours per week)
• Paid time off: up to four weeks per year based on scheduled hours, and up to 14 company-paid holidays
• Performance-based bonuses and incentives dependent on role type and job level