AstroTalentSpace Jobs

Senior Avionics FPGA Design & Verification Engineer - TeraWave Verified today

Blue Origin · 3 Locations · Electronics · first seen 2026-09-03
Apply at Blue Origin →

About TeraWave

Blue Origin is pioneering space-based communications with TeraWave, a revolutionary satellite network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation consists of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity worldwide.

The Role

As a Senior Avionics FPGA Design and Verification Engineer on the Spacecraft Systems team, you will develop vehicle avionics with Field Programmable Gate Arrays (FPGA) at the core for vehicle control and operation. You will design, develop, and verify high-performance avionics hardware for space flight vehicles, driving requirements definition, modeling, analysis, design, test, and production release of on-vehicle systems.

Your Responsibilities

  • Design and develop digital hardware architectures for high reliability satellite avionics
  • Create and implement RTL code for critical SoC blocks and interfaces
  • Contribute to architecture optimization for performance, power, and cost trade-offs
  • Collaborate on design verification to ensure robust and reliable designs
  • Participate in advanced verification techniques including Assertion-Based Verification, Universal Verification Methodology, and Constrained Random Verification
  • Support prototype development for early validation
  • Document design specifications, architecture decisions, and implementation details
  • Participate in design reviews and technical discussions with cross-functional teams
  • Troubleshoot and debug complex digital design issues
  • Implement interfaces between digital hardware and firmware/software components
  • Research and evaluate new architectural approaches to meet evolving requirements

Minimum Qualifications

  • B.S. or higher in Electrical Engineering, Computer Engineering, or related discipline
  • 7+ years of experience in digital design and SoC architecture
  • Proficiency in SystemVerilog or Verilog for RTL implementation
  • Experience with SoC integration and interface design
  • Understanding of digital timing and synchronization concepts
  • Knowledge of industry-standard bus protocols (AXI, AHB, etc.)
  • Familiarity with synthesis tools and RTL-to-gates methodology
  • Experience with simulation and debugging of complex digital systems
  • Strong background in Field Programmable Gate Arrays (FPGA) and FPGA tool flow
  • Solid knowledge of simulation-based test using Questasim and evaluation of code coverage metrics

Compensation

Base pay range varies by location:

  • CA applicants: $156,802.00 - $219,522.45
  • CO applicants: $144,179.00 - $201,849.90
  • WA applicants: $156,802.00 - $219,522.45

Benefits

  • Medical, dental, vision, basic and supplemental life insurance
  • Paid parental leave
  • Short and long-term disability
  • 401(k) with company match of up to 5%
  • Education Support Program
  • Stock options for all regular employees (20+ hours/week)
  • Paid time off: up to 4 weeks per year based on scheduled hours, plus up to 14 company-paid holidays
  • Performance-based bonuses may be available

Requirements

Applicants must be a U.S. citizen or national, U.S. permanent resident (Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. A standard background check is required for all positions.