Senior DSP Fixed-Point Design Engineer Verified today
About the role
Blue Origin is developing TeraWave, a satellite communications network delivering 6 Tbps symmetrical data speeds globally. We seek a Senior DSP Fixed-Point Design Engineer to join our Silicon Development team in Kraków, Poland.
You will convert complex floating-point DSP algorithms into bit-true, cycle-accurate fixed-point models and optimized hardware architectures. You will bridge Systems and Algorithm teams with RTL designers and Design Verification, ensuring silicon meets the reliability and performance standards of human spaceflight.
What you will do
- Convert floating-point algorithms to fixed-point models using MATLAB, C++, or Python, maintaining bit-true alignment with hardware requirements
- Conduct quantization noise analysis, finite word-length studies, and trade-off analyses balancing area, power, and performance against SNR/EVM degradation
- Define hardware-friendly DSP architectures including pipeline structures, word lengths, rounding modes, overflow/saturation logic, and scaling strategies for radiation-tolerant environments
- Collaborate with RTL designers to implement hardware blocks: multipliers, CORDIC engines, FFTs, and digital filters; review RTL against bit-true reference models
- Generate fixed-point test vectors and golden reference models to support Design Verification and post-silicon validation
- Drive micro-architectural optimizations for low power, high throughput, and minimal silicon area in custom accelerators for guidance, navigation, communications, and sensor processing
- Work across systems engineering, avionics, and software teams to ensure DSP implementations satisfy end-to-end system requirements
What we need
Required
- BS or MS in Electrical Engineering, Computer Engineering, or closely related field
- 5+ years hands-on experience in silicon/ASIC/FPGA development focused on DSP hardware implementation
- Deep understanding of fixed-point arithmetic, quantization noise modeling, overflow/underflow handling, dynamic range management, and scaling techniques
- Expert proficiency in MATLAB, C++, and/or Python (NumPy/SciPy) for algorithm modeling, simulation, and automated verification
- Strong foundation in digital signal processing: FIR/IIR filter design, FFT architectures, multi-rate signal processing, and automatic gain control (AGC)
- Ability to document and communicate complex technical trade-offs to engineering peers and program leadership
Preferred
- Experience with High-Level Synthesis tools such as Catapult HLS or Vivado/Vitis HLS
- Familiarity with RTL design (Verilog/SystemVerilog) and front-end ASIC flows (synthesis, timing closure, formal verification)
- Exposure to wireless communications standards (5G/6G, Wi-Fi) or AI/ML hardware accelerator design
If you don't meet every desired qualification, we encourage you to apply. You may be the right candidate for this or other roles.