Senior DSP Fixed-Point Design Engineer Verified today

About the Role

Blue Origin is pioneering space-based connectivity with TeraWave, a satellite communications network delivering symmetrical data speeds of up to 6 Tbps globally. We are seeking a Senior DSP Fixed-Point Design Engineer to join our Silicon Development team in Kraków, Poland.

You will bridge theoretical signal processing algorithms and high-performance, area- and power-efficient hardware implementations for aerospace applications. You will convert floating-point algorithmic models into optimized fixed-point architectures and collaborate with RTL and Design Verification teams to deliver silicon meeting the demanding reliability standards of human spaceflight.

Key Responsibilities

• Convert complex floating-point DSP algorithms from Systems and Algorithm teams into bit-true, cycle-accurate fixed-point models using MATLAB, C++, or Python.
• Conduct rigorous quantization noise analysis, finite word-length effect studies, and trade-off analyses balancing area, power, and performance against SNR/EVM degradation.
• Define and document hardware-friendly DSP architectures, including pipeline structures, optimal word lengths, rounding modes, overflow/saturation logic, and scaling strategies for radiation-tolerant or fault-tolerant environments.
• Partner with RTL designers to guide implementation of hardware blocks including multipliers, CORDIC engines, FFTs, and digital filters. Review RTL code against bit-true reference models.
• Generate comprehensive fixed-point test vectors and golden reference models to support pre-silicon Design Verification and post-silicon validation.
• Drive micro-architectural optimizations targeting low power consumption, high throughput, and minimal silicon area for custom hardware accelerators in guidance, navigation, communications, and sensor processing.
• Work across systems engineering, avionics, and software teams to ensure DSP hardware implementations satisfy end-to-end system requirements.

Basic Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or closely related field.
• 5+ years of hands-on experience in silicon/ASIC/FPGA development with strong focus on DSP hardware implementation.
• Deep understanding of fixed-point arithmetic, quantization noise modeling, overflow/underflow handling, dynamic range management, and scaling techniques.
• Expert proficiency in MATLAB, C++, and/or Python (NumPy/SciPy) for algorithm modeling, simulation, and automated verification workflows.
• Strong foundation in digital signal processing, including FIR/IIR filter design, FFT architectures, multi-rate signal processing, and automatic gain control (AGC).
• Ability to clearly document and communicate complex technical trade-offs to engineering peers and program leadership.

Preferred Qualifications

• Experience with High-Level Synthesis tools such as Catapult HLS or Vivado/Vitis HLS.
• Familiarity with RTL design (Verilog/SystemVerilog) and front-end ASIC flows (synthesis, timing closure, formal verification).
• Exposure to wireless communications standards (5G/6G, Wi-Fi) or AI/ML hardware accelerator design.

Applications accepted on an ongoing basis until requisition closes.