Senior High-Speed PCB Engineer - TeraWave Verified today

About TeraWave

Blue Origin is developing TeraWave, a revolutionary satellite communications network with optically interconnected satellites in low and medium Earth orbit (LEO/MEO). The constellation will deliver symmetrical data speeds up to 6 Tbps globally.

Your responsibilities

High-Speed PCB Design and Signal Integrity

• Lead physical design of complex, multi-layer PCBs for the TeraWave network switch platform.
• Perform pre- and post-layout signal integrity analysis: SerDes lanes, DDR memory buses, high-density Ethernet switch interconnects.
• Apply controlled impedance routing for differential pairs and single-ended high-speed signals.
• Optimize via structures to minimize stub lengths in high-density designs.
• Select dielectric materials to control differential pair skew and impedance variation.
• Define PCB layer stack-ups with fabricators, specifying laminate materials, prepreg, copper weights, via structures, and coupon testing.
• Develop 3D electromagnetic (EM) simulation models of critical PCB structures, extracting broadband S-parameter models.
• Perform SI simulation to validate eye margins, crosstalk levels, and correlate results with physical measurements.
• Apply de-embedding techniques, VNA measurements, and TDR analysis to correlate simulation with hardware.

DDR Memory Interface Design

• Design DDR4 and DDR5 memory subsystems, understanding fly-by topology, write leveling, read/write training, and memory controller constraints.
• Account for PCB routing limitations: byte lane grouping, skew budgets, address/command fly-by routing, return current management, trace length matching.
• Demonstrate DDR compliance through laboratory measurements.

SerDes, Microprocessor, and High-Speed Interface PCB Design

• Design PCB layouts for high-speed SerDes interfaces: 10GbE, 25GbE, 40GbE, 100GbE, and beyond.
• Implement PCB designs for microprocessors and SoCs (ARM, RISC-V, MPSoC), managing high pin-count BGA packages, escape routing, via-in-pad usage, and power delivery networks.
• Optimize high-speed connector and backplane interfaces for minimum via stub and maximum channel insertion loss margin.

Power Integrity Design and Verification

• Architect low-impedance power delivery networks (PDNs) for high-current, noise-sensitive devices: switch ASICs, microprocessors, FPGAs, DDR memory.
• Perform PDN simulation using frequency-domain tools to verify decoupling capacitor placement, value selection, and plane resonance suppression.
• Execute PI measurements: VNA-based PDN impedance, time-domain load transient validation, switching noise characterization.
• Design multi-stage LC filtering and high-PSRR LDO post-regulation stages.
• Apply plane-splitting, via stitching, and decoupling placement strategies to prevent power-plane noise coupling.

PCB Design for Manufacturability (DFM) and Design for Testability (DFT)

• Apply rigorous DFM practices: via and pad structure selection, copper feature sizing, annular ring, clearance rules for IPC Class 2/3 space hardware.
• Implement component placement and routing strategies supporting automated optical inspection (AOI), X-ray inspection, and solder paste printing yield.
• Implement comprehensive DFT strategies: boundary scan (JTAG) chain architecture, dedicated test point placement for in-circuit test (ICT) and flying probe access, built-in self-test (BIST) hooks, test connectors and loopback provisions for high-speed interface validation.
• Work closely with PCB fabricators and contract manufacturers during design review cycles.
• Demonstrate compliance through laboratory measurements.

Electromagnetic Compatibility (EMC)

• Apply working knowledge of EMC design principles: conducted emissions, radiated emissions, conducted susceptibility, radiated susceptibility.
• Implement PCB-level mitigation strategies: filter component placement and selection, chassis ground stitching via placement, guard trace strategies, shielding, bulk decoupling and filtering.
• Demonstrate compliance through laboratory measurements.

Hardware Integration and Validation

• Lead hardware bring-up and validation of the TeraWave switch PCB: power sequencing, high-speed interface eye diagram characterization, BER testing, component environmental testing.
• Develop and execute hardware validation test plans covering SI/PI measurements, functional test, environmental screening.
• Support resolution of complex PCB-related hardware issues, integrating findings into PCB design guidelines.
• Collaborate with firmware and software teams on BSP integration, device driver bring-up, and hardware-software interface debug.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 7 or more years of experience in high-speed PCB design and hardware development in a product development environment.
• Demonstrated track record of designing and shipping complex, high-speed multi-layer PCBs from concept through high volume production.
• Deep expertise in signal integrity analysis: pre/post-layout SI simulation, eye diagram analysis, crosstalk characterization, physical layer correlation measurements.
• Hands-on experience with advanced PCB manufacturing technologies.
• Proven experience designing high speed memory interfaces.
• Hands-on experience designing PCB layouts for serializers and deserializers (SerDes) at data rates of 10 Gbps and above.
• Experience designing microprocessor and SoC PCB implementations.
• Strong expertise in power integrity (PI) design and verification: PDN target impedance analysis, decoupling network simulation, physical PDN impedance measurement and validation.
• Experience with PCB design for manufacturability (DFM) and design for testability (DFT).
• Excellent technical documentation and communication skills.
• Background in production hardware: supply chain coordination, PCB fabrication vendor management, assembly oversight, yield optimization for high-reliability assemblies.

Preferred qualifications

• Master's degree in Electrical or Computer Engineering.
• 10 or more years of relevant high-speed PCB design experience.
• Experience designing electronics for thermal conduction environments (no convective cooling) for space-deployed hardware: thermal heat sink design, component placement.
• Experience with radiation effects on electronics (SEE, TID, displacement damage) and associated PCB-level and component-level mitigation techniques for the target orbital environment, including redundancy to meet mission reliability requirements.
• Hands-on environmental qualification testing experience (Thermal vacuum - TVAC, vibration, EMI/EMC) correlated to PCB design decisions.

Compensation and benefits

Base pay range for Washington applicants: $156,802.00 - $219,522.45. Other site ranges may differ.

Benefits include: medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with company match up to 5%, education support program, stock options for regular employees (20+ hours/week), up to four weeks paid time off per year, up to 14 company-paid holidays.

Employment eligibility

Applicants for employment at Blue Origin must be a U.S. citizen or national, U.S. permanent resident (Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Background checks are required for all positions.