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Senior Modem SOC Design Engineer - TeraWave Verified today

Blue Origin · 4 Locations · RF & Comms · first seen 2026-10-30
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About TeraWave

Blue Origin is developing TeraWave, a satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth, serving enterprise, data center, and government users.

Role

As a Senior Modem SOC Design Engineer on the ASIC Engineering SOC Team, you will design digital hardware for the TeraWave System on Chip. You will own RTL design for modem datapath and PHY blocks, implement signal processing hardware, and build out the Arm compute subsystem, debug, and IO infrastructure. This is an individual contributor role with no direct reports.

Responsibilities

  • Design RTL in Verilog or System Verilog for modem datapath and PHY blocks
  • Define microarchitecture from satellite communication system specifications and performance requirements
  • Implement signal processing hardware including filters, FFT, equalizers, and forward error correction
  • Develop Arm compute subsystem logic including AXI interconnect and SRAM controller integration
  • Integrate debug subsystem components using Arm CoreSight architecture and associated trace infrastructure
  • Design general purpose IO subsystem logic and associated configuration register interfaces
  • Integrate subsystem and SOC level blocks including clock and reset architecture
  • Support synthesis, timing constraint development, and timing closure with physical design teams

Minimum Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
  • Minimum 5 years of experience in digital ASIC or SOC RTL design
  • Experience with RTL design in Verilog or System Verilog for modem or PHY blocks
  • Experience with Arm compute subsystem design including AXI interconnect and SRAM controllers
  • Experience implementing signal processing hardware such as filters, FFT, or forward error correction

Preferred Qualifications

  • Master's degree in Electrical Engineering, Computer Engineering, or related technical field
  • Experience with debug subsystem design using Arm CoreSight components
  • Experience defining microarchitecture from communication system and algorithm specifications
  • Experience with SOC level integration including bus fabric, clock, and reset architecture
  • Experience with synthesis, timing constraint development, and timing closure support
  • Experience with LPDDR6 or other high speed memory interface subsystems
  • Experience with gigabit Ethernet or 25G high speed serial interface subsystems

Compensation

Base pay range for CA and WA applicants: $230,398.00 to $322,556.85. Other site ranges may differ.

Requirements

Applicants must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Benefits

  • Medical, dental, vision, basic and supplemental life insurance
  • Paid parental leave
  • Short and long-term disability
  • 401(k) with company match up to 5%
  • Education Support Program
  • Stock options for regular employees working at least 20 hours/week
  • Up to four weeks paid time off per year and up to 14 company-paid holidays