Senior Product Engineer, Modem SOC — TeraWave Verified today

About the Role

Blue Origin is pioneering space-based communications with TeraWave, a multi-orbit satellite constellation delivering symmetrical data speeds up to 6 Tbps globally. You will own the production release of the Modem SOC - a highly integrated 5G NR NTN System-on-Chip for satellite and non-terrestrial network digital communications. Sitting at the intersection of product engineering, test engineering, and validation engineering, you will guide the modem SOC from tape-out through qualification, characterization, engineering validation, and high-volume production, directly influencing schedule attainment, yield, and cost structure.

Key Responsibilities

• Take full ownership of the Modem SOC product release, guiding the chip from tape-out compliance through production qualification while ensuring adherence to internal development processes and JEDEC standards.
• Formulate and execute characterization and qualification plans across all major subsystems.
• Drive validation and test engineering groups for measurements and data collection; own statistical analysis, qualification, ATE correlation, production test-limit setting, and datasheet parameter validation.
• Lead boot subsystem bring-up and validation: secure boot, QSPI NOR flash, EMMC NAND flash, root-of-trust authentication flows, and OTA firmware update verification.
• Own power domain and DVFS characterization: power-mode transitions, per-domain voltage/frequency scaling, power gating, wake/sleep latency, and GALS clocking architecture validation for space mission power budgets.
• Lead L2/L3 crypto DMA and security subsystem validation: M2M crypto throughput, key management, interrupt routing, and integrity-fail response.
• Develop and validate ATE test plans and coverage in partnership with test engineers, including DFT-based structural test (scan, BIST, JTAG) and functional test coverage for modem PHY and compute subsystems.
• Own failure analysis across the production lifecycle, coordinating with design, OSATs, and labs to root-cause yield, reliability, and field issues and drive corrective actions.
• Review NPI hardware designs - load boards, characterization boards, and probe cards - for modem SOC bring-up.
• Spearhead cost reductions through yield improvement, test-time optimization, and ATE coverage rationalization.
• Manage excursions, including low-yield events, RMAs, and in-field anomalies.
• Operate as the key interface between the NPI team and backend operations and OSATs.
• Define KPIs for modem SOC production health, monitor ongoing performance, and deliver regular reporting to program and operations leadership.
• Continuously identify process enhancements for the NPI flow, with emphasis on modem-specific bring-up complexity across compute, modem PHY, and high-speed interface domains.
• Act as a mentor to junior team members, fostering technical and professional growth.

Required Qualifications

• BSEE or equivalent and 7+ years of IC product engineering / product development experience, including bringing complex digital or mixed-signal SOCs from definition to production release.
• Demonstrated experience owning product releases through characterization, qualification, and reliability testing on advanced-node ASICs.
• Hands-on expertise with high-speed digital SOC testing: SerDes interface characterization, DDR memory validation, compute subsystem bringup, and ATE test development.
• Advanced knowledge of IC manufacturing processes, DFT methodologies (scan, BIST, JTAG), and failure analysis techniques.
• Strong statistical analysis capability with proficiency in JMP, Gauge R&R, limit setting, and DOE methodology.
• Proficiency in Python or similar scripting language for test automation, data collection, and analysis.

Preferred Qualifications

• MSEE or advanced degree in Electrical Engineering or related field.
• Extensive experience with compute SOC or modem ASIC NPI, including ownership of schedule, planning, and budget.
• Deep expertise in 5G NR modem PHY testing or validation in satellite / NTN applications, including L1 channelization, beam-slice datapath, and full-duplex TX/RX characterization.
• Hands-on experience with 112G PAM4 SerDes characterization: eye diagram analysis, jitter decomposition, BER floor testing, and daisy-chain link margin.
• Direct experience with LPDDR5x or LPDDR6 bring-up, ECC validation, throughput characterization, and margin testing.
• Experience with Arm compute subsystem NPI: Neoverse core bringup, CMN-700 mesh, SMMU/GIC validation, and interrupt subsystem verification.
• Experience with secure boot validation, root-of-trust authentication flows, and hardware security module testing.
• Experience with timing and synchronization interface validation: PPS, PTP/IEEE 1588, SyncE, or GNSS reference inputs.
• Experience with DVFS and multi-domain power management testing for advanced-node SOCs.
• Experience developing or qualifying radiation-tolerant / radiation-hardened products for space applications.
• Direct experience interfacing with OSATs and backend operations through NPI bringup and production ramp for advanced-node digital or mixed-signal ASICs.
• Experience mentoring early-career engineers.

Location and Travel

Based onsite in Austin, TX. A temporary remote work exception is approved while the Austin site is being developed. Travel expected up to 10% of the time. Relocation provided.

Additional Information

Interviews will include a technical assessment.