AstroTalentSpace Jobs

SLD FPGA Verification Engineer III - Lunar Permanence Verified today

Blue Origin · 2 Locations · Electronics · first seen 2026-09-03
Apply at Blue Origin →

You will participate in verification of FPGA-based solutions within the Sustaining Lunar Development program's avionics, guidance, and navigation group. This includes requirements development with design engineers, verification through formal methods, UVM-based simulation, and on-target testing.

You will build high-reliability, safety-critical avionics solutions for the Human Landing System (HLS) vehicle. Experience with DO-254 is a plus.

Key Responsibilities

  • Perform requirements-based verification of FPGAs using Universal Verification Methodology (UVM)
  • Create comprehensive verification and validation plans that encompass functional and system-level verification
  • Develop IP, subsystem, and system-level testbench and tests to achieve required coverage goals
  • Write directed and random test cases
  • Document plans and procedures
  • Generate reports in support of design certification to a high Design Assurance Level (DAL)
  • Develop detailed test plans, run regressions, collect coverage matrices, and report progress to the program
  • Review verification and validation results against coverage goals
  • Write, analyze, and achieve coverage metrics
  • Debug issues between RTL design and testbench or test case

Required Qualifications

  • BS or MS in Electrical Engineering, Computer Engineering, or closely related field
  • 5 or more years experience verifying FPGAs or ASICs
  • In-depth experience using RTL simulation tools such as Siemens QuestaSim, ModelSim, or equivalent
  • In-depth knowledge of System Verilog and Universal Verification Methodology (UVM)
  • Expertise in developing testbench environments and verification components (Monitor, Scoreboard, Driver, Agent) from scratch
  • Understanding of different types of coverage, cover classes, and cover points
  • Experience with predictive testbench components, functional coverage, and assertions
  • Experience with constrained random verification
  • Experience with the Register Abstraction Layer
  • Strong debugging skills to isolate issues between RTL design and testbench or test case

Desired Qualifications

  • Familiarity with AXI protocols, PCIe, Ethernet, SPI, or I2C interfaces
  • Debugging FPGA/ASIC hardware and assisting with HW/SW integration
  • Managing regression and continuous integration infrastructure within GitLab
  • Knowledge of scripting languages such as Python, Perl, TCL, or Shell for automation
  • Working knowledge of NPR 7150.2, DO-254, or other safety-critical software standards

Compensation and Employment

Compensation range for Washington applicants: $130,706.00 to $182,987.70. Other site ranges may differ.

This is a full-time position. Applicants must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Benefits

  • Medical, dental, vision, basic and supplemental life insurance
  • Paid parental leave
  • Short and long-term disability
  • 401(k) with company match up to 5%
  • Education Support Program
  • Stock options for regular employees (20+ hours/week)
  • Paid time off: up to 4 weeks per year and up to 14 company-paid holidays
  • Performance-based bonuses and benefits (subject to company discretion)