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Sr ASIC Design Engineer - TeraWave Verified today

Blue Origin · 3 Locations · Electronics · first seen 2026-10-01
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About TeraWave

Blue Origin is pioneering space-based communications with TeraWave, a satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO).

Role Overview

This is a foundational role within the Silicon Systems Development team. You will design and develop the silicon that enables the future of space-based communication.

Key Responsibilities

  • Design and develop FPGAs, digital ASICs, and/or mixed-signal ASICs
  • Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog)
  • Develop verification methodologies and test benches for block and system-level verification
  • Create and execute test plans, develop test harnesses, and implement coverage models
  • Conduct timing analysis, noise analysis, and other signoff checks
  • Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering
  • Support lab integration and troubleshooting activities
  • Resolve design issues and drive solutions for timing, congestion, and other implementation challenges

Basic Qualifications

  • 7+ years of experience in ASIC design and implementation
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
  • Experience with FPGA and ASIC design
  • Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)
  • Experience with Linux development environment
  • Experience with design verification and test bench development

Preferred Skills and Experience

  • Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
  • Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration and test)
  • Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs
  • Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM)
  • Strong object-oriented programming and scripting skills (Python, TCL, Perl)
  • Experience with physical design flows and industry-standard EDA tools
  • Experience with RTL2GDSII physical design and signoff flows
  • Knowledge of deep sub-micron FinFET and CMOS technologies
  • Experience with DFT/Scan/MBIST/LBIST methodologies
  • Experience mentoring junior engineers

Compensation

Base pay range for CA applicants: $249,235.00 to $348,928.65. Other site ranges may differ.

Location

This role will be onsite in either Cupertino, CA, San Diego, CA, or Austin, TX. It is approved for temporary remote work exception while local sites are being developed in San Diego and Austin.

Employment Requirements

Applicants must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted as a refugee or granted asylum.

Benefits

  • Medical, dental, vision, basic and supplemental life insurance
  • Paid parental leave
  • Short and long-term disability
  • 401(k) with company match of up to 5%
  • Education Support Program
  • Stock options for all regular employees (20+ hours per week)
  • Up to four weeks paid time off per year and up to 14 company-paid holidays
  • Potential bonuses based on role type and job level