GPU System Reliability Engineer Lead Verified today
About the Role
Deploying high-performance GPU compute in Low Earth Orbit introduces fundamentally different fault conditions than ground datacenters. When a fault occurs 500km above Earth, the system must detect, classify, contain, and recover from it autonomously. You will own the end-to-end RAS validation strategy for GPU server systems, working directly with GPU and HBM silicon partners to analyze failures, characterize fault propagation paths, and ensure detection and recovery mechanisms function correctly.
What You Will Do
- Lead RAS validation strategy and execution for GPU server platforms, including fault injection, detection coverage, and recovery verification.
- Partner directly with GPU system designers to analyze hardware failures, review silicon errata, and align on fault handling requirements for DDR, HBM, CPU, and GPU subsystems.
- Characterize fault propagation paths from hardware detection through firmware and OS layers, and validate that error signals are correctly classified, logged, and acted upon.
- Validate BMC and out-of-band management visibility into hardware health events via IPMI, Redfish, and MCTP/PLDM protocols.
- Debug complex failure modes spanning GPU and CPU architecture, memory subsystems, PCIe/NVLink fabric, and system management firmware.
- Drive root-cause analysis for RAS failures discovered during validation and work with partners to provide input on platform design decisions that affect fault detection and serviceability.
- Define RAS coverage metrics and maintain traceability from hardware fault models to test coverage.
- Collaborate with firmware, software, and platform teams to validate OS-level error handling, ACPI error interfaces (EINJ, BERT, HEST), and runtime error recovery flows.
What You Need
- Bachelor's degree in Electrical Engineering or related discipline.
- 5+ years of experience in hardware validation, platform reliability engineering, or silicon validation on server-class compute systems.
- Deep understanding of CPU and GPU architecture, including memory subsystems (DDR, HBM), cache hierarchies, and interconnect fabrics (PCIe, NVLink, XGMI).
- Strong knowledge of RAS concepts: error detection and correction (ECC), fault containment, error propagation, machine check architecture (MCA/MCI), and recovery mechanisms.
- Hands-on experience with fault injection methodologies at hardware, firmware, and software levels.
- Familiarity with system management interfaces including BMC, IPMI, Redfish, and MCTP/PLDM.
- Experience working directly with silicon vendors or ODM partners on hardware failure analysis and RAS gap closure.
- Strong scripting skills in Python or equivalent for test automation and log analysis.
Compensation
Salary: $150,000 to $225,000 annually, depending on qualifications and experience.
- Equity in Cowboy Space Corp.
- Medical, dental, and vision insurance
- 401(k) retirement savings plan
- Paid time off
- 10 paid holidays per calendar year
- Paid parental leave
- Relocation assistance if applicable
- Daily lunch in office and fully stocked kitchen
ITAR Requirement
To comply with U.S. space technology export regulations (ITAR), applicants must be a U.S. citizen, lawful permanent resident, protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain required authorizations from the U.S. Department of State.