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Principal ASIC Physical Design Engineer Verified today

K2 Space · Seattle, WA · Electronics · first seen 2026-07-16
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The Role

Lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow - from RTL handoff to GDSII - and collaborate with architecture, RTL design, DFT, and packaging teams. You'll manage external physical design partners, drive tool and flow decisions, and ensure first-pass silicon success in advanced FinFET technologies.

In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, physical verification, and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area.
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors.
  • Work with EDA vendors to debug and optimize tool flows.
  • Support chip bring-up and debug through collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore or outsourced physical design teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert to teach, grow, and mentor others in the team.

Preferred Qualifications

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits

  • Base salary range: $190,000 - $280,000 plus equity.
  • Comprehensive benefits including paid time off, medical, dental, vision coverage, life insurance, and paid parental leave.