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Senior ASIC Design Verification Engineer Verified today

K2 Space · Seattle, WA · Electronics · first seen 2026-07-16
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The Role

Verify the functionality, performance, and robustness of custom silicon designs for K2's satellites. You will define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.

Responsibilities

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog and UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Contribute to advancement of design verification methodologies and improvements.
  • Engage external IP providers and verification partners when needed.

Qualifications

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
  • Proficiency with a simulation tool (VCS, Xcelium, Questa), waveform debug tool (Verdi, SimVision), coverage tool, and scripting languages (Python, Perl, TCL).
  • Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
  • Understanding of several industry-standard interfaces (APB, AHB, AXI).
  • Familiarity with embedded processor-based designs and firmware or bare metal coding (C, C++).

Nice to Have

  • Experience developing and integrating reference models.
  • Understanding of low power verification.