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Senior ASIC Physical Design Engineer Verified today

K2 Space · Seattle, WA · Electronics · first seen 2026-07-16
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The Role

You will implement advanced SoCs that power next-generation satellite and space systems. Working closely with architecture, RTL, verification, and packaging teams, you will contribute to the full physical design flow from synthesis to GDSII. You will be key to achieving timing closure, optimizing PPA, and supporting design integration with external partners.

In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. Within two years, you will have contributed to cutting-edge SoCs that fly in space.

Responsibilities

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place and route, CTS, STA, and physical verification.
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
  • Develop and maintain scripts and automation to improve flow efficiency and consistency.
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
  • Assist in chip-level integration, ECOs, and tapeout preparation.
  • Contribute to methodology development, tool evaluation, and flow documentation.
  • Support your product through production and spaceflight.

Required Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 5-10 years of experience in ASIC physical design for complex SoCs.
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
  • Strong understanding of timing analysis, power optimization, and physical verification flows.
  • Experience with hierarchical or flat SoC design methodologies.
  • Familiarity with FinFET technologies.
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Preferred Qualifications

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience with sign-off through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits

  • Base salary range: $170,000 to $250,000 plus equity in the company.
  • Salary based on knowledge, skills, education, and experience level.
  • Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and additional perks.

Export Compliance

This role requires access to information and items controlled by U.S. export control regulations, including ITAR. You must either be a U.S. person as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.