Senior FPGA Engineer II Verified today

Rocket Lab · Tucson, AZ · Electronics · first seen 2026-09-06

About Rocket Lab

Rocket Lab is the end-to-end space company building rockets, spacecraft, and critical subsystems. Our Space Systems division enables more than 1,700 missions including interplanetary exploration, in-space manufacturing, and national security initiatives. We work with NASA, the Space Development Agency, and the U.S. Space Force.

About Rocket Lab Optical Systems

Rocket Lab Optical Systems solves mission-critical space domain and Intelligence, Surveillance, and Reconnaissance challenges for Department of Defense and Intelligence Community customers. We deliver innovative electro-optical and infrared systems for responsive, scalable sensing solutions across all orbital domains.

The Role

As a Senior FPGA Engineer II, you will support Tranche 3 of the U.S. Space Development Agency's Proliferated Warfighter Space Architecture by designing FPGAs for advanced electro-optical space payloads in Tucson, AZ.

What You'll Do

  • Work with the hardware design team on requirements
  • Complete FPGA logic design, coding, simulation, and testing
  • Support hardware and software development teams in bring-up and test of products
  • Provide subject-matter expertise on design and automated test development procedures to customers and production support team
  • Perform research and analysis of customer specifications, datasheets, and manuals to determine design approach and feasibility
  • Execute debugging of the design in the lab
  • Perform synthesis, implementation, and timing analysis

Required Qualifications

  • Bachelor's degree in computer engineering, electrical engineering, or equivalent discipline
  • 8+ years of experience writing FPGA firmware from scratch in VHDL
  • Ability to obtain and maintain a U.S. Government security clearance

Desirable Qualifications

  • Experience with Xilinx/AMD Versal architecture
  • Experience with FPGAs and embedded systems in a radiation environment, including SEU/SEL impact and mitigation
  • Experience in FPGA- or ASIC-based image processing algorithms
  • Experience creating IP from scratch in RTL and integrating existing IP into RTL and block designs
  • Familiarity with C, Python, or MATLAB and translating algorithms from scripted language to HDL
  • Experience with software interfaces including interrupts and DMA
  • Experience with DDR4, Aurora, and high-speed transceiver design and verification
  • Familiarity with AXI Stream and AXI Memory Mapped interfaces
  • PCB design and schematic capture with tools such as Altium Designer

Physical Requirements

This position requires close vision, distance vision, peripheral vision, depth perception, and the ability to focus. You will regularly sit, use hands and fingers, operate computer keyboard and controls, and communicate verbally and in writing. You must be physically able to commute to buildings. Work may include prolonged sitting, standing, walking, computer work, and occasional exposure to moderate levels of noise, dust, and fumes in production areas.

Employment Requirements

To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), you must be a U.S. citizen, lawful U.S. permanent resident, or have other eligible ITAR authorization status.