Sr. ASIC Design Engineer (Silicon Engineering) Verified today
About the role
SpaceX is developing next-generation ASICs for deployment in Starlink satellites and ground infrastructure worldwide. You will work with cross-disciplinary teams in systems, firmware, architecture, design, validation, and product engineering to deliver chips that expand network performance and bring connectivity to underserved communities.
What you will do
- Evaluate architectural trade-offs based on features, performance requirements and system limitations
- Define micro-architecture and implement RTL in Verilog/SystemVerilog
- Integrate designs at top level and deliver fully verified, synthesis and timing clean designs
- Work closely with verification teams to ensure comprehensive coverage
- Provide timing constraints and support physical implementation (synthesis, timing closure, formality checks)
- Participate in silicon bring-up and validation
Basic requirements
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- 5+ years of experience in RTL implementation
Preferred experience
- Clock domain crossing and power optimization
- ASIC/SoC system integration
- Embedded CPU subsystems
- Standard bus protocols (AXI, AHB, etc.)
- High-speed and low-power design techniques
- Scripting (Python or similar)
- EDA tools including HDL simulators and lint tools
Additional requirements
- Ability to work extended hours or weekends for mission-critical deadlines
- U.S. citizen, national, lawful permanent resident, refugee, or asylee under 8 U.S.C. 1157/1158, or eligible to obtain required State Department authorizations (ITAR)